Nuevo MEMORIA APACER DDR4 2133 U-DIMM 8GB 1024 x 8 (EL.08G2R.GDH) Ver más grande

MEMORIA APACER DDR4 2133 U-DIMM 8GB 1024 x 8 (EL.08G2R.GDH)

EL.08G2R.GDH

Nuevo

MEMORIA APACER DDR4 2133 U-DIMM 8GB 1024 x 8 (EL.08G2R.GDH)

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96,00 € impuestos incl.

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Functionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supportedFunctionality and operations comply with the DDR4 SDRAM datasheet
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Write CRC is supported at all speed grades
DBI (Data Bus Inversion) is supported(x8)
CA parity (Command/Address Parity) mode is supported
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